RERI Architecture Specification

Augments Reliability, Availability, and Serviceability (RAS) features in the SoC with a standard mechanism for reporting errors by means of a memory-mapped register interface to enable error reporting. Additionally, this specification supports software-initiated error logging, reporting, and testing of RAS handlers. Lastly, this specification provides maximal flexibility to implement error handling and coexists with RAS frameworks defined by other standards such as PCIe and CXL.