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ISA Specifications default
  • Volume I: RISC-V Unprivileged ISA Specification
    • Unprivileged Architecture
    • Preamble
    • Preface
    • Introduction
    • RV32I Base Integer Instruction Set
    • RV32E and RV64E Base Integer Instruction Sets, Version 2.0
    • RV64I Base Integer Instruction Set
    • "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0
    • "Zicsr", Extension for Control and Status Register (CSR) Instructions, Version 2.0
    • "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0
    • "Zihintntl" Extension for Non-Temporal Locality Hints, Version 1.0
    • "Zihintpause" Extension for Pause Hint, Version 2.0
    • "Zimop" Extension for May-Be-Operations, Version 1.0
    • "Zicond" Extension for Integer Conditional Operations, Version 1.0.0
    • "M" Extension for Integer Multiplication and Division, Version 2.0
    • "A" Extension for Atomic Instructions, Version 2.1
    • "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01
    • "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0
    • "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0
    • RVWMO Memory Consistency Model, Version 2.0
    • "Ztso" Extension for Total Store Ordering, Version 1.0
    • "CMO" Extensions for Base Cache Management Operation ISA, Version 1.0.0
    • "F" Extension for Single-Precision Floating-Point, Version 2.2
    • "D" Extension for Double-Precision Floating-Point, Version 2.2
    • "Q" Extension for Quad-Precision Floating-Point, Version 2.2
    • "Zfh" and "Zfhmin" Extensions for Half-Precision Floating-Point, Version 1.0
    • "BF16" Extensions for for BFloat16-precision Floating-Point, Version 1.0
    • "Zfa" Extension for Additional Floating-Point Instructions, Version 1.0
    • "Zfinx", "Zdinx", "Zhinx", "Zhinxmin" Extensions for Floating-Point in Integer Registers, Version 1.0
    • "C" Extension for Compressed Instructions, Version 2.0
    • "Zc*" Extension for Code Size Reduction, Version 1.0.0
    • "B" Extension for Bit Manipulation, Version 1.0.0
    • "V" Standard Extension for Vector Operations, Version 1.0
    • Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1
    • Cryptography Extensions: Vector Instructions, Version 1.0
    • Control-flow Integrity (CFI)
    • RV32/64G Instruction Set Listings
    • ISA Extension Naming Conventions
    • Appendix A: RVWMO Explanatory Material, Version 0.1
    • Appendix B: Formal Memory Model Specifications, Version 0.1
    • Appendix C: Vector Assembly Code Examples
    • Appendix D: Calling Convention for Vector State (Not authoritative - Placeholder Only)
  • Volume II: RISC-V Privileged ISA Specification
    • Privileged Architecture
    • Preamble
    • Preface
    • Introduction
    • Control and Status Registers (CSRs)
    • Machine-Level ISA, Version 1.13
    • "Smstateen/Ssstateen" Extensions, Version 1.0
    • "Smcsrind/Sscsrind" Indirect CSR Access, version 1.0
    • "Smepmp" Extension for PMP Enhancements, Version 1.0
    • "Smcntrpmf" Cycke and Instret Privilege Mode Filtering, Version 1.0
    • "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0
    • "Smcdeleg" Counter Delegation Extension, Version 1.0
    • "Smdbltrp" Double Trap Extension, Version 1.0
    • "Smctr" Control Transfer Records Extension, Version 1.0
    • Supervisor-Level ISA, Version 1.13
    • "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0
    • "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0
    • "H" Extension for Hypervisor Support, Version 1.0
    • Control-flow Integrity(CFI)
    • "Ssdbltrp" Double Trap Extension, Version 1.0
    • Pointer Masking Extensions, Version 1.0.0
    • RISC-V Privileged Instruction Set Listings
    • History
    • Bibliography
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  • ISA Specifications
  • Volume II: RISC-V Privileged ISA Specification
  • Privileged Architecture

The RISC-V Instruction Set Manual

Volume II: Privileged Architecture

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Version 20250508: This document is in Ratified state.

Appendix D: Calling Convention for Vector State (Not authoritative - Placeholder Only) Preamble
  • ISA Specifications
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