"B" Extension for Bit Manipulation, Version 1.0.0

Add unsigned word

add.uw rd, rs1, rs2

zext.w rd, rs1 → add.uw rd, rs1, zero

This instruction performs an XLEN-wide addition between rs2 and the zero-extended least-significant word of rs1.

AND with inverted operand

andn rd, rs1, rs2

This instruction performs the bitwise logical AND operation between rs1 and the bitwise inversion of rs2.

Single-Bit Clear (Register)

bclr rd, rs1, rs2

This instruction returns rs1 with a single bit cleared at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

Single-Bit Clear (Immediate)

bclri rd, rs1, shamt

This instruction returns rs1 with a single bit cleared at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

Single-Bit Extract (Register)

bext rd, rs1, rs2

This instruction returns a single bit extracted from rs1 at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

Single-Bit Extract (Immediate)

bexti rd, rs1, shamt

This instruction returns a single bit extracted from rs1 at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

Single-Bit Invert (Register)

binv rd, rs1, rs2

This instruction returns rs1 with a single bit inverted at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

Single-Bit Invert (Immediate)

binvi rd, rs1, shamt

This instruction returns rs1 with a single bit inverted at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

Single-Bit Set (Register)

bset rd, rs1,rs2

This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

Single-Bit Set (Immediate)

bseti rd, rs1,shamt

This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

Carry-less multiply (low-part)

clmul rd, rs1, rs2

clmul produces the lower half of the 2·XLEN carry-less product.

Carry-less multiply (high-part)

clmulh rd, rs1, rs2

clmulh produces the upper half of the 2·XLEN carry-less product.

Carry-less multiply (reversed)

clmulr rd, rs1, rs2

clmulr produces bits 2·XLEN−2:XLEN-1 of the 2·XLEN carry-less product.

Count leading zero bits

clz rd, rs

This instruction counts the number of 0’s before the first 1, starting at the most-significant bit (i.e., XLEN-1) and progressing to bit 0. Accordingly, if the input is 0, the output is XLEN, and if the most-significant bit of the input is a 1, the output is 0.

Count leading zero bits in word

clzw rd, rs

This instruction counts the number of 0’s before the first 1 starting at bit 31 and progressing to bit 0. Accordingly, if the least-significant word is 0, the output is 32, and if the most-significant bit of the word (i.e., bit 31) is a 1, the output is 0.

Count set bits

cpop rd, rs

This instructions counts the number of 1’s (i.e., set bits) in the source register.

Count set bits in word

cpopw rd, rs

This instructions counts the number of 1’s (i.e., set bits) in the least-significant word of the source register.

Count trailing zeros

ctz rd, rs

This instruction counts the number of 0’s before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit (i.e., XLEN-1). Accordingly, if the input is 0, the output is XLEN, and if the least-significant bit of the input is a 1, the output is 0.

Count trailing zero bits in word

ctzw rd, rs

This instruction counts the number of 0’s before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit of the least-significant word (i.e., 31). Accordingly, if the least-significant word is 0, the output is 32, and if the least-significant bit of the input is a 1, the output is 0.

Maximum

max rd, rs1, rs2

This instruction returns the larger of two signed integers.

Unsigned maximum

maxu rd, rs1, rs2

This instruction returns the larger of two unsigned integers.

Minimum

min rd, rs1, rs2

This instruction returns the smaller of two signed integers.

Unsigned minimum

minu rd, rs1, rs2

This instruction returns the smaller of two unsigned integers.

Bitwise OR-Combine, byte granule

orc.b rd, rs

Combines the bits within each byte using bitwise logical OR. This sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.

OR with inverted operand

orn rd, rs1, rs2

This instruction performs the bitwise logical OR operation between rs1 and the bitwise inversion of rs2.

Pack the low halves of rs1 and rs2 into rd.

pack rd, rs1, rs2

The pack instruction packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half.

Pack the low bytes of rs1 and rs2 into rd.

packh rd, rs1, rs2

The packh instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd.

Pack the low 16-bits of rs1 and rs2 into rd on RV64.

packw rd, rs1, rs2

This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. This instruction only exists on RV64 based systems.

Byte-reverse register

rev8 rd, rs

This instruction reverses the order of the bytes in rs.

Reverse the bits in each byte of a source register.

brev8 rd, rs

This instruction reverses the order of the bits in every byte of a register.

Rotate Left (Register)

rol rd, rs1, rs2

This instruction performs a rotate left of rs1 by the amount in least-significant log2(XLEN) bits of rs2.

Rotate Left Word (Register)

rolw rd, rs1, rs2

This instruction performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.

Rotate Right

ror rd, rs1, rs2

This instruction performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of rs2.

Rotate Right (Immediate)

rori rd, rs1, shamt

This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

Rotate Right Word by Immediate

roriw rd, rs1, shamt

This instruction performs a rotate right on the least-significant word of rs1 by the amount in the least-significant log2(XLEN) bits of shamt. The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.

Rotate Right Word (Register)

rorw rd, rs1, rs2

This instruction performs a rotate right on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. The resultant word is sign-extended by copying bit 31 to all of the more-significant bits.

Sign-extend byte

sext.b rd, rs

This instruction sign-extends the least-significant byte in the source to XLEN by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.

Sign-extend halfword

sext.h rd, rs

This instruction sign-extends the least-significant halfword in rs to XLEN by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.

Shift left by 1 and add

sh1add rd, rs1, rs2

This instruction shifts rs1 to the left by 1 bit and adds it to rs2.

Shift unsigned word left by 1 and add

sh1add.uw rd, rs1, rs2

This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 1 place.

Shift left by 2 and add

sh2add rd, rs1, rs2

This instruction shifts rs1 to the left by 2 places and adds it to rs2.

Shift unsigned word left by 2 and add

sh2add.uw rd, rs1, rs2

This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 2 places.

Shift left by 3 and add

sh3add rd, rs1, rs2

This instruction shifts rs1 to the left by 3 places and adds it to rs2.

Shift unsigned word left by 3 and add

sh3add.uw rd, rs1, rs2

This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 3 places.

Shift-left unsigned word (Immediate)

slli.uw rd, rs1, shamt

This instruction takes the least-significant word of rs1, zero-extends it, and shifts it left by the immediate.

Place odd and even bits of the source register into upper and lower halves of the destination register, respectively.

unzip rd, rs

This instruction scatters all of the odd and even bits of a source word into the high and low halves of a destination word. It is the inverse of the zip instruction. This instruction is available only on RV32.

Exclusive NOR

xnor rd, rs1, rs2

This instruction performs the bit-wise exclusive-NOR operation on rs1 and rs2.

Byte-wise lookup of indices into a vector in registers.

xperm8 rd, rs1, rs2

The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8 8-bit elements. The rs2 register contains a vector of XLEN/8 8-bit indexes. The result is each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.

Nibble-wise lookup of indices into a vector.

xperm4 rd, rs1, rs2

The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4 4-bit elements. The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.

Zero-extend halfword

zext.h rd, rs

This instruction zero-extends the least-significant halfword of the source to XLEN by inserting 0’s into all of the bits more significant than 15.

Interleave upper and lower halves of the source register into odd and even bits of the destination register, respectively.

zip rd, rs

This instruction gathers bits from the high and low halves of the source word into odd/even bit positions in the destination word. It is the inverse of the unzip instruction. This instruction is available only on RV32.